Research Thrust 1: Semiconductor Growth and Integration

 

A central question in modern semiconductor technology is: how can we integrate high-performance crystalline materials onto technologically essential but fundamentally incompatible substrates like silicon, glass, or flexible foils? For decades, progress has been constrained by the principle of epitaxial growth, which requires a near-perfectly matched crystal lattice to serve as a template. This limitation has created a bottleneck for the monolithic integration of diverse materials needed for next-generation computing and sensing systems.

Our research addresses this challenge through the development of non-epitaxial growth techniques that circumvent the need for a lattice-matched substrate. Our initial work in Nature Communications first demonstrated that pristine, single-crystalline III-V semiconductors could be grown directly on amorphous substrates like silicon dioxide [1]. Subsequent research has focused on engineering this process for improved material quality, reliability, and systems compatibility. We have established that the optoelectronic quality of our Templated Liquid Phase (TLP) grown films is largely independent of the underlying buffer layers, indicating a high degree of process robustness [2]. We have also lowered the growth temperature to be compatible with back-end-of-line (BEOL) silicon CMOS processing (<400°C) [3] and have experimentally verified that the resulting films exhibit high charge-carrier mobilities comparable to conventionally grown materials [4].

This methodology was shown to be a general growth techniques, which allows for the fabrication of high-performance materials on a wide variety of substrates [5]. The flexibility of these techniques has enabled a diverse range of applications, from early demonstrations of low-cost solar cells on flexible foils [6] to more recent work integrating III-V semiconductors on CMOS-compatible metals for reconfigurable metasurfaces [7]. Taken together, these methods provide a pathway for the heterogeneous integration of compound semiconductors, enabling new device concepts that are not feasible with conventional epitaxial constraints.

 

Key Publications in Semiconductor Growth and Integration

 

1. Direct growth of single-crystalline III–V semiconductors on amorphous substrates

Chen, K., Kapadia, R., Harker, A., et al. Nature Communications 7, 10502 (2016). Link to Publication

• Key Scientific Result: Demonstration of a method for the direct, templated growth of single-crystalline III-V semiconductors (e.g., InAs) on amorphous substrates such as silicon dioxide (SiO_2).
• What Was Shown (Experiments): A novel templated growth technique was employed where the geometry of a nanoscale seed window defined the growth orientation. Cross-sectional Transmission Electron Microscopy (TEM) and electron diffraction were used to confirm the single-crystalline nature and high quality of the material grown on the amorphous surface.
• Relevance: This work provides a materials science solution for heterogeneous integration, enabling the potential for monolithic 3D structures that combine III-V optoelectronics with silicon-based circuits.

2. Buffer insensitive optoelectronic quality of InP-on-Si with templated liquid phase growth

Sarkar, D., Wang, W., Lin, Q., et al. & Kapadia, R. Journal of Vacuum Science & Technology B 36, 032902 (2018). Link to Publication

• Key Scientific Result: A study of the Templated Liquid Phase (TLP) growth of Indium Phosphide (InP), finding that the optoelectronic quality of the resulting film is largely independent of the underlying amorphous buffer layer’s properties.
• What Was Shown (Experiments): High-quality InP films were grown on several different amorphous dielectric buffer layers (e.g., SiO_2, SiN_x). Temperature-dependent and power-dependent photoluminescence (PL) spectroscopy was performed, revealing similar high quality (narrow linewidths, minimal non-radiative recombination) across the different buffers.
• Relevance: This result indicates a high degree of process robustness for the TLP method, relaxing the strict material constraints for buffer layers typically required in semiconductor growth and simplifying integration.

3. Low temperature growth of crystalline semiconductors on nonepitaxial substrates

Sarkar, D., Weng, S., Yang, D., et al. & Kapadia, R. Advanced Materials Interfaces 7, 1902191 (2020). Link to Publication

• Key Scientific Result: Demonstration of high-quality crystalline semiconductor (InP, InAs) growth on non-epitaxial substrates at temperatures below 400°C.
• What Was Shown (Experiments): The TLP process temperature was successfully lowered into a range compatible with back-end-of-line (BEOL) processing. Structural characterization via TEM confirmed the high crystalline quality of the films, and fabricated field-effect transistors exhibited good performance, indicating that the low-temperature process did not compromise electronic properties.
• Relevance: The reduction in thermal budget to below 400°C makes this growth technique compatible with BEOL CMOS processing, allowing for the integration of III-V materials without damaging pre-existing silicon circuitry.

4. High mobility large area single crystal III-V thin film templates directly grown on amorphous SiO2 on silicon

Tao, J., Sarkar, D., Weng, S., et al. & Kapadia, R. Applied Physics Letters 117, 042103 (2020). Link to Publication

• Key Scientific Result: Quantitative characterization of large-area, single-crystal III-V templates grown directly on amorphous SiO_2, confirming high charge carrier mobility.
• What Was Shown (Experiments): Large-area InAs templates were grown using the TLP method. Field-effect transistors were fabricated on these templates, and their electrical characteristics were measured. The devices exhibited electron mobilities comparable to those fabricated on conventionally grown, lattice-matched substrates, confirming the high electronic quality of the material.
• Relevance: The measured high mobility validates that the direct-growth method yields electronically sound films suitable for high-performance transistor applications.

5. Confined Liquid Phase Growth of Crystalline Compound Semiconductors on Any Substrate

Sarkar, D., Wang, W., Mecklenburg, M., et al. & Kapadia, R. ACS Nano 12, 5158–5166 (2018). Link to Publication

• Key Scientific Result: The development and generalization of the templated growth technique into a method termed “Confined Liquid Phase” (CLP) growth.
• What Was Shown (Experiments): The CLP technique was used to grow a variety of crystalline compound semiconductors on different non-native substrates, including various dielectrics and metals. Electron microscopy was used to confirm that the technique consistently produced high-quality crystalline material regardless of the underlying surface.
• Relevance: This method provides a generalized route for fabricating crystalline compound semiconductors on a wide variety of substrates, significantly expanding the possibilities for heterogeneous materials integration.

6. A direct thin-film path towards low-cost large-area III-V photovoltaics

Kapadia, R., Yu, Z., Wang, H. H., et al. Scientific Reports 3, 2275 (2013). Link to Publication

• Key Scientific Result: The initial demonstration of the thin-film vapor-liquid-solid (TF-VLS) growth mode to produce large-area, polycrystalline InP films on inexpensive metal foils.
• What Was Shown (Experiments): Polycrystalline InP films with large grain sizes (>100 µm) were grown on molybdenum foils. The optoelectronic quality was confirmed via photoluminescence, and the material was fabricated into functioning solar cell devices, which were characterized under illumination.
• Relevance: This early co-first author work demonstrated the potential of non-epitaxial growth for large-area applications like photovoltaics and served as a precursor to the development of single-crystalline growth techniques.

7. Monolithic III–V on Metal for Thermal Metasurfaces

Chae, H. U., Shrewsbury, B., Ahsan, R., et al. & Kapadia, R. ACS Nano 16, 18497–18502 (2022). Link to Publication

• Key Scientific Result: Successful monolithic integration of III-V semiconductor nanostructures directly onto CMOS-compatible metallic substrates.
• What Was Shown (Experiments): High-quality InP was grown using the CLP method on titanium nitride (TiN), a metal commonly used in silicon manufacturing. The resulting InP/TiN heterostructure was patterned and shown to function as an electrically tunable thermal metasurface, with its infrared emissivity modulated by an applied voltage.
• Relevance: This work expands the substrate compatibility of our growth techniques to include metals, enabling the fabrication of novel, monolithically integrated devices such as the demonstrated active optical and thermal components.